The present invention relates to signal detection and correction in the presence of noise. More particularly, the present invention relates to signal detection and correction in the presence of noise using phase locked loops.
When there is low signal to noise ratio (SNR), achieving accurate detection of signals is difficult due to significant amount of noise present with the signals. Typically under these conditions, error correction coding (ECC) can be used to recover the signals. However, timing recovery is a prerequisite for effective implementation of ECC. Phase locked loops (PLLs) provide timing recovery.
PLLs correct for timing phase error using a feedback loop, which permits timing recovery and synchronization for use of ECC. PLLs that are decision directed derive a reference signal from the detected information in order to perform phase error detection. The longer the wait for the reference signal, the more accurate the reference signal, and hence more accurate the phase error detection. However, too long of a wait for an accurate reference signal creates a large delay in the loop, which leads to performance loss. As a balance between relatively long delays in the feedback loop and accuracy of final output, conventional PLLs use a preliminary or early decision signal to form the reference signal. This preliminary decision signal is not as accurate as the final decision signal but is available sooner to minimize loop latencies. When the SNR is relatively high, the higher error rate typical in the preliminary decision signal (as opposed to the final decision signal) is not detrimental and the PLL provides adequate timing recovery. However, as the SNR decreases, the higher error rate typical in the preliminary decision signal results in the PLL losing phase lock, at which point the PLL is unable to provide phase error detection.
As the SNR decreases, the phase error or jitter increases, degrading PLL performance. As an example, when the noise level is high enough such that an error exists for approximately every 1,000 bits in the detected signal, conventional PLLs lose phase lock.
Thus, it would be beneficial for a PLL to minimize loop latencies. It would be beneficial for a PLL to use an early decision signal having characteristics of a later decision signal. It would be beneficial for a PLL to maintain phase lock at low SNRs. It would be beneficial for a playback device of a data storage unit to permit use of ECC at low SNRs by providing time recovery under a range of SNR conditions.